| Company |
Tektronix |
| Part Number |
mso_dpo_5000
|
| Form Factor |
portable |
|
Bandwidth |
350 MHz - 2GHz |
|
Price Ranges |
$10000 - $100000 |
|
OS (Windows or embedded) |
Windows 7 |
|
Max Sample Rate |
5 GS/sec - 10 GS/sec , 10 GS/sec - 50 GS/sec |
|
Channels |
5 GS/sec - 10 GS/sec , 10 GS/sec - 50 GS/sec |
|
Max Memory Depth |
125 M |
|
Waveform Update Rate/Max Trigger Rate |
250,000 wfms/sec |
|
Display size/Touch or non-touch screen |
10.4 in. XGA color, touchscreen display |
|
Vertical Resolution |
8 bits (> |
|
Instrument Integrations |
16-channel logic analyzer |
|
Trigger Modes |
Edge Positive, negative, or either slope on any channel or front-panel auxiliary input. Coupling includes DC, AC, HF reject, LF reject, and noise reject Glitch Trigger on or reject glitches of positive, negative, or either polarity. Programmable glitch width is 4 ns minimum to 8 s maximum Runt Trigger on a pulse that crosses one threshold but fails to cross a second threshold before crossing the first again Width Trigger on width of positive or negative pulse either within or outside selectable limits (4 ns to 8 s) Timeout Trigger on an event which remains high, low, or either, for a specified time period (4 ns to 8 s) Transition Trigger on pulse edge rates that are faster or slower than specified. Slope may be positive, negative, or either Setup/Hold Trigger on violations of both setup time and hold time between clock and data present on any two input channels Pattern Trigger when any logical pattern of signals goes false or stays true for specified period of time (4 ns to 1 s). Pattern (AND, OR, NAND, NOR) specified for all analog and digital input channels defined as High, Low, or Don't Care Parallel Bus Trigger on specified data value on defined parallel bus State Any logical pattern of analog channels and digital channels (MSO models) clocked by edge on another channel. Trigger on rising or falling clock edge Video Trigger on all lines, specific line number, odd, even, or all fields on NTSC, PAL, SECAM, and HDTV 480p/60, 576p/50, 875i/60, 720p/30, 720p/50, 720p/60, 1080/24sF, 1080i/50, 1080p/25, 1080i/60, 1080p/24, 1080p/25, 1080p/50, 1080p/60, Bi-level, Tri-level Trigger Sequences Main, Delayed by Time, Delayed by Events. All sequences can include separate horizontal delay after the trigger event to position the acquisition window in time A/B Sequence Event Trigger Types Edge Trigger Delay by Time 4 ns to 8 s Trigger Delay by Events 1 to 4,000,000 events Visual Trigger Trigger on up to 8 user-specified areas, including rectangle, triangle, trapezoid, hexagon, and user-specified shapes on any of the analog channels I 2C (Optional) Provided as part of Opt. SR-EMBD. Trigger on Start, Repeated Start, Stop, Missing ACK, Address (7 or 10 bit), Data, or Address and Data on I2C buses up to 10 Mb/s SPI (Optional) Provided as part of Opt. SR-EMBD. Trigger on Slave Select, Idle Time, or Data (1-16 words) on SPI buses up to 10 Mb/s CAN (Optional) Provided as part of Opt. SR-AUTO. Trigger on Start of Frame, Type of Frame (Data, Remote, Error, or Overload), Identifier, Data, Identifier and Data, EOF, Missing Ack, Bit Stuff Error, and CRC Error on CAN buses up to 1 Mb/s LIN (Optional) Provided as part of Opt. SR-AUTO. Trigger on Sync, Identifier, Data, Identifier and Data, Wakeup Frame, Sleep Frame, and Error on LIN buses up to 1 Mb/s FlexRay (Optional) Provided as part of Opt. SR-AUTO. Trigger on Indicator Bits (Normal, Payload, Null, Sync, Startup), Cycle Count, Header Fields (Indicator Bits, Identifier, Payload Length, Header CRC, and Cycle Count), Identifier, Data, Identifier and Data, End Of Frame, and Error on FlexRay buses up to 10 Mb/s MIL-STD-1553 (Optional) Provided as part of Opt. SR-AERO. Trigger on Sync, Command Word, Status Word, Data Word, Idle Time, and Error on MILSTD-1553 buses up to 1 Mb/s Ethernet (Optional) Provided as part of Opt. SR-ENET. Trigger on Start of Packet, MAC Address, MAC Q-tag, MAC Length/Type, MAC Data, IP Header, TCP Header, TCP/IPV4 Data, End of Packet, and FCS(CRC) Error on 10BASE-T and 100BASE-TX buses. RS-232/422/485/UART (Optional) Provided as part of Opt. SR-COMP. Trigger on Start Bit, End of Packet, Data, and Parity Error up to 10 Mb/s Datasheet Trigger system 14 www.tektronix.com USB 2.0 Low Speed |
| Data can be further specified to trigger on ≤, , ≥, != a particular data value, or inside or outside a range. Handshake Packet Trigger – Any handshake type, ACK, NAK, STALL. Special Packet Trigger – Any special type, Reserved. Error Trigger – PID Check, CRC5 or CRC16, Bit Stuffing. USB 2.0 Full Speed |
(Optional) Provided as part of Opt. SR-USB. Trigger on Sync, Reset, Suspend, Resume, End of Packet, Token (Address) Packet, Data Packet, Handshake Packet, Special Packet, Error. Token Packet Trigger – Any token type, SOF, OUT, IN, SETUP |
| Data can be further specified to trigger on ≤, , ≥, != a particular data value, or inside or outside a range. Handshake Packet Trigger – Any handshake type, ACK, NAK, STALL. Special Packet Trigger – Any special type, PRE, Reserved. Error Trigger – PID Check, CRC5 or CRC16, Bit Stuffing. USB 2.0 High Speed |
(Optional) Provided as part of Opt. SR-USB. Trigger on Sync, Reset, Suspend, Resume, End of Packet, Token (Address) Packet, Data Packet, Handshake Packet, Special Packet, Error. Token Packet Trigger – Any token type, SOF, OUT, IN, SETUP |
| Data can be further specified to trigger on ≤, , ≥, != a particular data value, or inside our outside a range. Handshake Packet Trigger – Any handshake type, ACK, NAK, STALL, NYET. Special Packet Trigger – Any special type, ERR, SPLIT, PING, Reserved. SPLIT packet components that can be specified include |
Hub Address Start/Complete – Don't Care, Start (SSPLIT), Complete (CSPLIT) Port Address Start and End bits – Don't Care, Control/Bulk/Interrupt (Full-speed Device, Low-speed Device), Isochronous (Data is Middle, Data is End, Data is Start, Data is All) Endpoint Type – Don't Care, Control, Isochronous, Bulk, Interrupt Error Trigger – PID Check, CRC5, CRC16, Any. Trigger Sequences Main, Delayed by Time, Delayed by Events. All sequences can include separate horizontal delay after the trigger event to position the acquisition window in time A/B Sequence Event Trigger Types Edge Trigger Delay by Time 4 ns to 8 s Trigger Delay by Events 1 to 4,000,000 events Visual Trigger Trigger on up to 8 user-specified areas, including rectangle, triangle, trapezoid, hexagon, and user-specified shapes on any of the analog channels I2C (Optional) Provided as part of Opt. SR-EMBD. Trigger on Start, Repeated Start, Stop, Missing ACK, Address (7 or 10 bit), Data, or Address and Data on I2C buses up to 10 Mb/s SPI (Optional) Provided as part of Opt. SR-EMBD. Trigger on Slave Select, Idle Time, or Data (1-16 words) on SPI buses up to 10 Mb/s CAN (Optional) Provided as part of Opt. SR-AUTO. Trigger on Start of Frame, Type of Frame (Data, Remote, Error, or Overload), Identifier, Data, Identifier and Data, EOF, Missing Ack, Bit Stuff Error, and CRC Error on CAN buses up to 1 Mb/s LIN (Optional) Provided as part of Opt. SR-AUTO. Trigger on Sync, Identifier, Data, Identifier and Data, Wakeup Frame, Sleep Frame, and Error on LIN buses up to 1 Mb/s FlexRay (Optional) Provided as part of Opt. SR-AUTO. Trigger on Indicator Bits (Normal, Payload, Null, Sync, Startup), Cycle Count, Header Fields (Indicator Bits, Identifier, Payload Length, Header CRC, and Cycle Count), Identifier, Data, Identifier and Data, End Of Frame, and Error on FlexRay buses up to 10 Mb/s MIL-STD-1553 (Optional) Provided as part of Opt. SR-AERO. Trigger on Sync, Command Word, Status Word, Data Word, Idle Time, and Error on MIL-STD-1553 buses up to 1 Mb/s Ethernet (Optional) Provided as part of Opt. SR-ENET. Trigger on Start of Packet, MAC Address, MAC Q-tag, MAC Length/Type, MAC Data, IP Header, TCP Header, TCP/IPV4 Data, End of Packet, and FCS(CRC) Error on 10BASE-T and 100BASE-TX buses. RS-232/422/485/UART (Optional) Provided as part of Opt. SR-COMP. Trigger on Start Bit, End of Packet, Data, and Parity Error up to 10 Mb/s USB 2.0 Low Speed |
| , ≥, != a particular data value, or inside or outside a range. Handshake Packet Trigger – Any handshake type, ACK, NAK, STALL. Special Packet Trigger – Any special type, Reserved. Error Trigger – PID Check, CRC5 or CRC16, Bit Stuffing. USB 2.0 Full Speed |
(Optional) Provided as part of Opt. SR-USB. Trigger on Sync, Reset, Suspend, Resume, End of Packet, Token (Address) Packet, Data Packet, Handshake Packet, Special Packet, Error. Token Packet Trigger – Any token type, SOF, OUT, IN, SETUP |
| , ≥, != a particular data value, or inside or outside a range. Handshake Packet Trigger – Any handshake type, ACK, NAK, STALL. Special Packet Trigger – Any special type, PRE, Reserved. Error Trigger – PID Check, CRC5 or CRC16, Bit Stuffing. USB 2.0 High Speed |
(Optional) Provided as part of Opt. SR-USB. Trigger on Sync, Reset, Suspend, Resume, End of Packet, Token (Address) Packet, Data Packet, Handshake Packet, Special Packet, Error. Token Packet Trigger – Any token type, SOF, OUT, IN, SETUP |
| , ≥, != a particular data value, or inside our outside a range. Handshake Packet Trigger – Any handshake type, ACK, NAK, STALL, NYET. Special Packet Trigger – Any special type, ERR, SPLIT, PING, Reserved. SPLIT packet components that can be specified include |
Hub Address Start/Complete – Don't Care, Start (SSPLIT), Complete (CSPLIT) Port Address Start and End bits – Don't Care, Control/Bulk/Interrupt (Full-speed Device, Low-speed Device), Isochronous (Data is Middle, Data is End, Data is Start, Data is All) Endpoint Type – Don't Care, Control, Isochronous, Bulk, Interrupt Error Trigger – PID Check, CRC5, CRC16, Any. Note |
|
Time Base Range |
–10 divisions to 1000 s |
|
Time Scale Accuracy |
±5 ppm over any ≥1 ms interval |
|
Footprint |
5U |
